1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Related Art
FBC (Floating Body Cell) memory devices are semiconductor memory devices expected recently as memories replacing 1T (Transistor)-1C (Capacitor) DRAMs. According to the FBC memory device, an FET (Field Effect Transistor) with a floating body (hereinafter, also body) is formed on an SOI (Silicon On Insulator) substrate, and data “1” or data “0” is stored depending on the number of majority carriers accumulated in the body. A state that a small number of holes (majority carriers) are accumulated in the body is indicated as the data “0”. A state that a large number of holes are accumulated in the body is indicated as the data “1”.
A technique for having two adjacent memory cells share a bit line contact or a source line contact in an FBC has been developed to downscale memory chips (see JP-A 2006-301377 (KOKAI)). In the memory described in JP-A 2006-301377 (KOKAI), to reduce disturb during data “0” write, a potential of an unselected word line connected to cells which share a source line with cells connected to a selected word line is made to be lower than potentials of other unselected word lines during the write operation.
When the data “1” is selectively written in memory cells, however, a high level potential is applied to a bit line in a selected column. Thus, data in “0” cells connected to the unselected word line sharing the source line with the selected word line and the bit line in the selected column may be subject to disturb by GIDL (Gate Induced Drain Leakage). This is because when the unselected word line sharing the source line with the selected word line has a low level potential and the bit line in the selected column has a high level potential, holes are easily accumulated in the body of the “0” cell.